Memristors, phase-change materials and new emerging technologies for neuromorphic systems

9:00-10:15 Intro, Implementation and Computations

Electronic and Biological Memristors

Aurel A. Lazar

Aurel presented a brief outline of the underlying characteristics of current- and voltage controlled memristors. He provided explicit examples of memristors arising in both electronics and neuroscience. He derived the charge-flux relationship for the 'HP memristor" and depicted the same relationship for the Sodium and Potassium gating variables associated with the Hodgkin-Huxley neuron.

Following up on a question from the audience, he also showed why synapses arising in systems neuroscience are memristors.

Implementation of Neuromorphic Architectures with Memristors

Bernabe Linares-Barranco

The talk was about how to use voltage/flux driven memristors for spiking neuromorphic architectures exploiting STDP learning. It is critical that memristors have a dead zone within which they can be operated without any update. The next condition is that pre-synaptic and post-synaptic spikes have to converge at the memristor terminals. This way, the voltage drop at the memristor can be such that it goes bejond the dead zone when both spikes are close in time, so that memristor conductance can be updated according to an STDP like learning function. Given a specific memristor with given process/technological parameters, the specific STDP learning funtion can be modulated by playing the spikes shapes. It is important to highlight that memristors would implement a multiplicative type of STDP, in particular, a quadratic type, which has not been studied carefully in the computational literature. We explained that simulations have been performed that demonstrate self-formation of orientation selective receptive fields when a V1 like architecture with random initial weights is trained using spiking visual data coming out of Tobi's retina (DVS).

The talk is a summary of the paper "On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex" which can be downloaded from:  http://www.frontiersin.org/neuromorphic_engineering/10.3389/fnins.2011.00026/abstract.

Computation with Memristors and Memcapacitors

Mika Laiho & Eero Lehtonen

Eero Lehtonen described memristive implication logic and proposed a potential application for it. Implication logic essentially allows to use a memristor both as a memory and a latch, thus making it possible to synthesize Boolean functions with memristors without the need of auxiliary CMOS logic circuitry. This in turn allows bitwise parallel logic processing directly at the memory. As an application an associative processor structure was studied, where the unit of information is a high dimensional vector represented by binary memristors. These vectors are processed using implication logic based hyperdimensional arithmetic.

Tobi posed the question why to use such architecture instead of standard associative memory + logic. An answer is that should part of the processing elements be faulty, the processing still remains robust when using hyperdimensional arithmetic. It also increases the uniformity of the hardware, which may be beneficial in the point of view of fabrication.

10:45-12:00 Devices and Comparison to Conventional Technology

Organic Bistable Devices and Synthetic Synapses

Robert Nawrocki

1. brief intro to polymer/organic electronics:

• organic (polymer) materials as opposed to in-organic materials
• many devices made: OPV, OLED, OFET, memristors/OBD
• advantages: low cost of production (solution processing, spin/spray coating, printing), physically flexible, non- or less toxic materials
• disadvantages: 30 or 40 years behind in-organic electronics, lower speeds of operation (due to physical characteristics), greater device variability (due to physical characteristics - greater variability in "molecule" allignment)

2. organic bistable devices (OBDs)

• sort of like a saturation-mode memristor (hysteresis curve)
• basic operation:
  • resistive switching explained via charge trapping
  • below Vth the device operates with Roff, typically about 1GOhm
  • after Vin > Vth, device turns on and resistance decreases to Ron ~10kOhm
  • device operates with Ron until Vin < -Vth, when device turns back off -> Roff
• modeling: with 2 resistors: Ron and Roff
• possible use:
  • binary, synthetic synapse
  • memory device (cross bar)
  • implication logic

3. introduction to Synthetic Neural Network (SNN) - network of non-spiking neurons

• function that describes neuron: y=gamma (Sigma (x_i * w_i))
  • multiplication (synapse): x_i * w_i
  • summation (soma): Sigma ()
  • activation (soma): gamma ()
• SNN (OBDs, OFET, resistors)
• it works (activation function - output of neuron)
• verification:
  • simulation: WH, wall-following robot
  • emulation (resistors, 2 resistors for OBD (with only one connected), MOSFET): Structured Computational Polymers

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QUESTIONS:

- what's the frequency of OBD switching?

• about 1 ms

- what happens to OBD's resistance when power is removed?

• if the device was in OFF state, then R=Roff. but, if device was in ON state, then R=Ron.

Phase Change Materials

Martin Salinga

Notes on Slide 26 of pdf file on this wiki page.

Brief introduction into the working principle of phase change materials (illustration: top right corner of the slide)

- Two (meta-)stable phases around room temperature: amorphous and crystalline

- Strong property contrast: poorly conductive amorphous phase and highly conductive crystalline phase

- Rapid switching between phases by thermal excitation:

--Moderate heating brings material into temperature regime of fast crystallization (atoms are mobilized enough to find their way into the energetically more favorable crystalline state)

--For amorphization disorder is created by melting. Crystallization is inhibited by rapid cooling through the regime of fast crystallization.

Typical device architecture (illustration of a vertical cell architecture in top left corner of the slide)

- Two terminal device

- Phase Change material with a Top and a Bottom Electrode

- Heat is introduced by an electrical current via Joule heating

Multi-Level-storage

- possible by variable ratio of amorphous and crystalline volume (still cross section of a vertical cell in top left corner)

- control over 16 discrete resistance levels has been realized in phase change electronic memory cells (see histogram in the center of the slide)

- continuous resistance levels also possible.

Current-Voltage-characteristic (I-V-curve: center top)

- purely electronic switching from amorphous OFF to amorphous ON state

- crystallization induced by high temperature due to high currents

Programming behavior of phase change cells (figure middle right):

- subcritical voltage pulses do not change the resistance

- followed by stepwise crystallization (reduction of resistance)

- gradual increase of amorphous fraction by increasing pulse amplitude

promising spatial scaling behaviour:

- Crossbar arrays with diode-like accessing device in the crosspoint. Realized by Intel (figures at the bottom)

- Area per cell: almost 4 times F^{2 (F=Feature-size)}

- 3D-stacking of crossbar arrays feasible

Storing synaptic weights in phase change memory cells seems straight forward already today. Phase Change Memory is already in the market (Samsung). Other companies have experience with electronic memories based on phase change materials, too: IBM, Macronix, Intel, STMicroelectronics, Numonyx, Micron, NXP.

Advantage: very high device density.

Also STDP-learning of phase change cells is already proposed in a patent by IBM.

General remark:

Besides/instead of realizing neuromorphic hardware combining only standard devices (i.e. devices that are already available), ask device physicists for new devices that are inherently providing the functionality you need. This way a much higher spatial device density and likely also significantly lower power consumption should be possible.

=> What is your wish list?

Comparison against Silicon Technology

'Hasler'

Prof. Hasler performed a thoughtful comparison between achievable performance with memristors and present (and near future) commercial flash based solutions for both, plain memory (storage) applications and neuromorphic type systems.